- Dnotitia’s first-generation VDPU ASIC samples are back from fab, with chip-level characterization in progress and silicon-based evaluations planned for Q4 2026
- In FPGA-based evaluations, a four-card VDPU server delivered up to 5.77x the vector-search throughput of a dual-socket CPU server, while freeing up most of the host CPU and memory for the application
- VDPU integrates with Dnotitia’s Seahorse vector database and widely used vector-search software including Milvus, FAISS and hnswlib, and the company is expanding server-scale evaluations with system, storage, memory and vector database partners.
SANTA CLARA, Calif., Sept. 18, 2026 /PRNewswire/ — Dnotitia Inc. (Dnotitia), an AI data infrastructure and semiconductor company, today announced that the first ASIC samples of its Vector Data Processing Unit (VDPU) have returned from fabrication, with chip-level characterization now underway. At AI Infra Summit 2026, held Sept. 15-17 at the Santa Clara Convention Center, the company showcased a server-scale VDPU architecture designed for vector retrieval workloads in retrieval-augmented generation (RAG) and agentic AI.
Dnotitia Booth at AI Infra Summit 2026
The showcase followed the company’s first public display of its VDPU chip and accelerator card at the Future of Memory and Storage (FMS) 2026, where Dnotitia received a Best of Show Award, and marked the next step from chip-level demonstration to server-scale evaluation.
On Dnotitia’s FPGA evaluation platform, a server equipped with four VDPU cards delivered up to 5.77x the vector-search throughput of the same software stack running on a dual-socket CPU-only server, while maintaining equal or better recall. In a 4,096-dimensional multimodal workload, VDPU reduced host CPU use during index building by 92% and host memory by 73%, freeing host CPU resources for applications. All performance figures were measured on the FPGA platform and do not represent final ASIC performance.
“Agentic AI is shifting the AI infrastructure bottleneck from model compute toward retrieval,” said Se-Hyun Yang, Chief Technology Officer of Dnotitia. “As models search and verify information repeatedly, retrieval needs its own processing layer. VDPU is designed to give CPU capacity back to applications and keep GPU HBM focused on model execution. At AI Infra Summit, we showcased VDPU at server scale and opened discussions with infrastructure partners around evaluation and integration.”
The FPGA platform has been validated with FAISS, Milvus and hnswlib across brute-force KNN, IVF, NSW and HNSW indexes. Beyond the stacks already ported to the FPGA platform, Dnotitia plans to support a broader range of vector libraries and databases on the ASIC so that VDPU can work with the environments customers already run.
Dnotitia’s first-generation VDPU ASIC is currently undergoing chip-level characterization. The company plans to begin ASIC-based VDPU evaluations in Q4 2026. Dnotitia is targeting up to 10x vector-search performance versus a CPU-based server with its VDPU ASIC-based server.
During the summit, Se-Hyun Yang presented “Rethinking AI Infrastructure with Dedicated Vector Silicon,” outlining the architecture and performance results behind VDPU. Dnotitia also met with prospective customers and infrastructure partners at Booth 205 to discuss VDPU evaluations, proof-of-concept projects and potential integration into existing server, storage, and AI infrastructure.
Following the event, the company is continuing discussions with server, storage, memory and semiconductor companies, as well as vector database providers and AI framework developers, as it expands server-scale VDPU evaluations and prepares for ASIC-based evaluation in Q4 2026.
